The encyclopedia · Engineering & Operations · Technical decision · 2013–2024
Samsung stacked NAND cells vertically in 2013 and doubled density past the shrink limit
In August 2013 Samsung mass-produced the industry's first 3D V-NAND, stacking 24 layers of cells vertically and doubling density over planar 20nm chips.
Samsung Electronics
The solution
By the early 2010s NAND flash makers were squeezing cells into ever-smaller nodes, but below roughly 20nm the cells interfered with each other — electrons leaked, endurance fell, and planar miniaturization was hitting a wall.
On 6 August 2013 Samsung announced it had begun mass production of the industry's first 3D Vertical NAND, a 128Gb chip. Its own '3D cylindrical CTF cell structure' and '3D vertical stacking process' stacked 24 layers like a building, with holes etched through the layers to connect electrodes; density more than doubled versus 20nm-class chips.
The vertical design reduced cell-to-cell interference, roughly doubling write speed, lifting write endurance from 2x to 10x by product, and halving power consumption. It was the first of many generations — 32 layers in 2014, then 48, and by 2024 the 9th generation at 286 layers.
Why it worked
- Vertical stacking evades the miniaturization limit
- CTF cells cut interference between stacked layers
- Density gains without expensive new lithography
- First-mover mass production set the industry standard
What can be applied
When the shrink runs into physics, change the dimension: going vertical sidesteps the lithography race entirely and hands the leader a density advantage planar rivals cannot copy quickly.
Aftermath
V-NAND became the industry's standard architecture: Samsung pushed to 32 layers (2014), 48 layers (2015) and later 9th-generation 286-layer products (2024), with competitors forced to follow. The 2013 launch is remembered as the opening of the 3D memory era.
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